quarta-feira, 20 de abril de 2011

ICMC oferece curso de compiladores para FPGA

O Instituto de Ciências Matemáticas e de Computação (ICMC), da USP São Carlos, oferecerá o curso Compiler Transformations and Mapping Techniques for Reconfigurable Architectures, a ser ministrado pelo professor Pedro Diniz, da University of Southern California, nos Estados Unidos.

O curso ocorrerá nos dias 3, 4 e 5 de maio e será ministrado em português. As inscrições são gratuitas e devem ser feitas até o dia 30 de abril pelo e-mail emarques@icmc.usp.br.

Objetivos do curso (em inglês):
This course provides a helpful structure for practitioners or graduate students in the area of computer science and electrical and computer engineering to effectively transform and map computations expressed in high-level programming languages such as C to reconfigurable architectures. We will cover many compiler code transformations and mapping techniques with specific examples of their application thereby helping attendees to bridge the gap between the software compilation and the hardware compilation and synthesis domains. In the course we will study and explore the mapping of computations from C to hardware description languages such as VHDL/Verilog and evaluate using a series of laboratory examples on an existing FPGA-based board alternative implementations and corresponding performance trade-offs.

This course is primarily intended for researchers and graduate students in the areas of study of hardware compilation and advanced computing architectures in the fields of Electrical and Computer Engineering and Computer Science. Particular emphasis will be given to applications examples and transformations that explore concepts such as latency and throughput, of key importance in application areas such as image/signal processing or robotics. As it focuses on the specific topic of compilation from high-level program descriptions to reconfigurable architectures, this course can easily support advanced compiler and computer architecture courses related to reconfigurable computing.

Estrutura do curso
This short seminar-like course will be structured into three days as outlined below. During the mornings (4 hours) we will provide and the theoretical basis for the hands-on afternoon laboratory sessions. In these experimental sessions (4 hours) the attendees will use real computations examples and map the corresponding computations to state-of-the-art FPGA-based hardware devices. In this mapping process we will explore alternative design implementations for three key computation kernels from the domain of signal and image processing as well as more symbolic-oriented decision tree kernel computation.

Terça, 3 de maio
Lecture: 8:30 AM to 12:00 (noon)
- Motivation and Introduction to Reconfigurable Computing: FPGAs and Embedded Systems
- Compilation and Synthesis Flow: Basic Concepts of CFG and DFG: Bridging the representation gap
- Illustrative Example of Computation Mapping from C to VHDL
- Data-Flow Representation
- Computation-Oriented Mapping and Scheduling
- Data-Oriented mapping and Transformations
- Translation to Hardware
- Synchronization and Communication of data and execution.
Laboratory: 1:00 PM to 4:00 PM
- Using an existing FPGA-based board – the Altera X
- Synthesizing a simple project exploiting custom numeric formats for an embedded application.

Quarta-feira, 4 de maio
Lecture: 8:30 AM to 12:00 (noon)
- High-level Code Transformations
- Bit-Level Transformations
- Code-level transformations
- Loop-level transformations
- Data-oriented transformations
- SOBEL edge detection illustrative example
Laboratory: 1:00 PM to 4:00 PM
- Mapping the SOBEL edge detection with a set of transformations.
- Evaluation of performance for various transformed variants of the code

Quinta-feira, 5 de maio
Lecture: 8:30 AM to 12:30 (noon)
- Design-Space Exploration
- Metrics of Performance: Space and Execution Time.
- Which transformations to apply: guiding principles
- Timing and throughput: Loop transformations and the space restrictions
- SOBEL edge detection illustrative example
- Summary
Laboratory: 2:00 PM to 6:00 PM
- Using the SOBEL edge detection with a set of transformations.
- Design space exploration for various constraints.

Sobre o palestrante
Prof. Pedro Diniz
Foto: site da USC
Dr. Pedro Diniz received his M.S. in Electrical and Computer Engineering from the Technical University in Lisbon, Portugal and his Ph.D. from the University of California, Santa Barbara in Computer Science in 1997.From 1997 until 2007 he was a researcher with the University of Southern California’s Information Sciences Institute (USC/ISI) as a Researcher and became an Assistant Professor of Computer Science at the University of Southern California in Los Angeles, California.At USC/ISI was the technical lead of DARPA-funded and DoE-funded research projects, in particular in the DEFACTO project totaling $6M USD. The DEFACTO project combined the strengths of traditional parallelizing compilation approaches with commercially available EDA synthesis tools and lead to the development of a prototype compiler for the automatically mapping of image processing algorithms written in programming languages such as C to Field-Programmable-Gate-Array-based computing architectures. He is currently a scientific coordinator of a EU-funded STREP research project REFLECT that is building a compilation and synthesis infra-structure for design space exploration for multi-core FPGA-based designs. This project involves various academic partners as well as large and SME industrial partners in Europe. He has graduated 3 PhD students while at USC and authored or co-authored 10 internationally recognized scientific journal papers and over 40 international conference papers. He has participated in many scientific proposal review boards at the National Science Foundation (NSF) and the European Commission (EC). He is heavily involved in the scientific community having participated as part of the technical program committee of over 15 international conferences in the area of high-performance computing, reconfigurable and field-programmable computing.